Silicon Labs /Series0 /EFM32G /EFM32G890F128 /PRS /CH2_CTRL

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Interpret as CH2_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIGSEL 0 (NONE)SOURCESEL0 (OFF)EDSEL

SOURCESEL=NONE, EDSEL=OFF

Description

Channel Control Register

Fields

SIGSEL

Signal Select

SOURCESEL

Source Select

0 (NONE): No source selected

1 (VCMP): Voltage Comparator

2 (ACMP0): Analog Comparator 0

3 (ACMP1): Analog Comparator 1

6 (DAC0): Digital to Analog Converter 0

8 (ADC0): Analog to Digital Converter 0

16 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0

17 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1

18 (USART2): Universal Synchronous/Asynchronous Receiver/Transmitter 2

28 (TIMER0): Timer 0

29 (TIMER1): Timer 1

30 (TIMER2): Timer 2

40 (RTC): Real-Time Counter

41 (UART0): Universal Asynchronous Receiver/Transmitter 0

48 (GPIOL): General purpose Input/Output

49 (GPIOH): General purpose Input/Output

EDSEL

Edge Detect Select

0 (OFF): Signal is left as it is

1 (POSEDGE): A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

2 (NEGEDGE): A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

3 (BOTHEDGES): A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

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